Intel® Arria® 10 SX 270 FPGA
Specifications
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Essentials
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Product Collection
Intel® Arria® 10 SX SoC FPGA
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Marketing Status
Launched
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Launch Date
2013
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Lithography
20 nm
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Resources
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Logic Elements (LE)
270000
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Adaptive Logic Modules (ALM)
101620
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Adaptive Logic Module (ALM) Registers
406480
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Fabric and I/O Phase-Locked Loops (PLLs)
16
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Maximum Embedded Memory
17.4 Mb
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Digital Signal Processing (DSP) Blocks
830
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Digital Signal Processing (DSP) Format
Multiply, Multiply and Accumulate, Variable Precision, Fixed Point (hard IP), Floating Point (hard IP)
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Hard Processor System (HPS)
Dual-core Arm* Cortex*-A9
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Hard Memory Controllers
Yes
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External Memory Interfaces (EMIF)
DDR4, DDR3, QDR II, QDR II+, QDR IV, LPDDR3, DDR3L
I/O Specifications
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Maximum User I/O Count†
384
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I/O Standards Support
3.0 V LVTTL, 1.2 V to 3.0 V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL
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Maximum LVDS Pairs
168
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Maximum Non-Return to Zero (NRZ) Transceivers†
24
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Maximum Non-Return to Zero (NRZ) Data Rate†
17.4 Gbps
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Transceiver Protocol Hard IP
PCIe Gen3
Advanced Technologies
Package Specifications
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Package Options
F672, F780, F1152
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
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Ordering and spec information
Trade compliance information
- ECCN 3A991
- CCATS NA
- US HTS 8542390001
PCN Information
SR4FL
- 965334 PCN
SR45A
- 964972 PCN
SR457
- 964969 PCN
SR456
- 964968 PCN
SR455
- 964967 PCN
SR454
- 964966 PCN
SR453
- 964965 PCN
SR4EA
- 965288 PCN
SR459
- 964971 PCN
SR458
- 964970 PCN
SR44F
- 964938 PCN
SR4E7
- 965285 PCN
SR44E
- 964937 PCN
SR4E6
- 965284 PCN
SR48H
- 965085 PCN
SR4E5
- 965283 PCN
SR48G
- 965084 PCN
SR4E4
- 965282 PCN
SR4E3
- 965281 PCN
SRBDD
- 973480 PCN
SR4E2
- 965280 PCN
SRBDC
- 973479 PCN
SR4E1
- 965279 PCN
SRBDB
- 973478 PCN
SRBDA
- 973477 PCN
SR44N
- 964945 PCN
SR44M
- 964944 PCN
SR44L
- 964943 PCN
SR44K
- 964942 PCN
SR44J
- 964941 PCN
SR44H
- 964940 PCN
SR4E9
- 965287 PCN
SR44G
- 964939 PCN
SR4E8
- 965286 PCN
SR445
- 964928 PCN
SR444
- 964927 PCN
SR443
- 964926 PCN
SR442
- 964925 PCN
SR441
- 964924 PCN
SR440
- 964923 PCN
SR4DM
- 965265 PCN
SR43Z
- 964922 PCN
SR449
- 964932 PCN
SR448
- 964931 PCN
SR447
- 964930 PCN
SR47H
- 965051 PCN
SR47G
- 965050 PCN
SR47F
- 965049 PCN
SR47D
- 965047 PCN
SR47C
- 965046 PCN
SR47B
- 965045 PCN
SR47J
- 965052 PCN
SR434
- 964831 PCN
SR433
- 964820 PCN
SR432
- 964811 PCN
SR476
- 965040 PCN
SR431
- 964800 PCN
SR430
- 964784 PCN
SR47A
- 965044 PCN
SR42Z
- 964783 PCN
SR42Y
- 964765 PCN
SR42X
- 964759 PCN
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Processor System (HPS)
The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.